Major mode for editing Verilog code.
Uses keymap `verilog-mode-map', which is not currently defined.
See C-h f verilog-auto (M-x verilog-auto) for details on how
AUTOs can improve coding efficiency.
Use M-x verilog-faq for a pointer to frequently asked questions.
NEWLINE, TAB indents for Verilog code.
Delete converts tabs to spaces as it moves back.
Supports highlighting.
Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
with no args, if that value is non-nil.
Variables controlling indentation/edit style:
variable `verilog-indent-level' (default 3)
Indentation of Verilog statements with respect to containing block.
`verilog-indent-level-module' (default 3)
Absolute indentation of Module level Verilog statements.
Set to 0 to get initial and always statements lined up
on the left side of your screen.
`verilog-indent-level-declaration' (default 3)
Indentation of declarations with respect to containing block.
Set to 0 to get them list right under containing block.
`verilog-indent-level-behavioral' (default 3)
Indentation of first begin in a task or function block
Set to 0 to get such code to lined up underneath the task or
function keyword.
`verilog-indent-level-directive' (default 1)
Indentation of `ifdef/`endif blocks.
`verilog-cexp-indent' (default 1)
Indentation of Verilog statements broken across lines i.e.:
if (a)
begin
`verilog-case-indent' (default 2)
Indentation for case statements.
`verilog-auto-newline' (default nil)
Non-nil means automatically newline after semicolons and the punctuation
mark after an end.
`verilog-auto-indent-on-newline' (default t)
Non-nil means automatically indent line after newline.
`verilog-tab-always-indent' (default t)
Non-nil means TAB in Verilog mode should always reindent the current line,
regardless of where in the line point is when the TAB command is used.
`verilog-indent-begin-after-if' (default t)
Non-nil means to indent begin statements following a preceding
if, else, while, for and repeat statements, if any. Otherwise,
the begin is lined up with the preceding token. If t, you get:
if (a)
begin // amount of indent based on `verilog-cexp-indent'
otherwise you get:
if (a)
begin
`verilog-auto-endcomments' (default t)
Non-nil means a comment /* ... */ is set after the ends which ends
cases, tasks, functions and modules.
The type and name of the object will be set between the braces.
`verilog-minimum-comment-distance' (default 10)
Minimum distance (in lines) between begin and end required before a comment
will be inserted. Setting this variable to zero results in every
end acquiring a comment; the default avoids too many redundant
comments in tight quarters.
`verilog-auto-lineup' (default 'declarations)
List of contexts where auto lineup of code should be done.
Variables controlling other actions:
`verilog-linter' (default surelint)
Unix program to call to run the lint checker. This is the default
command for M-x compile-command and M-x verilog-auto-save-compile.
See M-x customize for the complete list of variables.
AUTO expansion functions are, in part:
M-x verilog-auto Expand AUTO statements.
M-x verilog-delete-auto Remove the AUTOs.
M-x verilog-inject-auto Insert AUTOs for the first time.
Some other functions are:
M-x verilog-complete-word Complete word with appropriate possibilities.
M-x verilog-mark-defun Mark function.
M-x verilog-beg-of-defun Move to beginning of current function.
M-x verilog-end-of-defun Move to end of current function.
M-x verilog-label-be Label matching begin ... end, fork ... join, etc statements.
M-x verilog-comment-region Put marked area in a comment.
M-x verilog-uncomment-region Uncomment an area commented with M-x verilog-comment-region.
M-x verilog-insert-block Insert begin ... end.
M-x verilog-star-comment Insert /* ... */.
M-x verilog-sk-always Insert an always @(AS) begin .. end block.
M-x verilog-sk-begin Insert a begin .. end block.
M-x verilog-sk-case Insert a case block, prompting for details.
M-x verilog-sk-for Insert a for (...) begin .. end block, prompting for details.
M-x verilog-sk-generate Insert a generate .. endgenerate block.
M-x verilog-sk-header Insert a header block at the top of file.
M-x verilog-sk-initial Insert an initial begin .. end block.
M-x verilog-sk-fork Insert a fork begin .. end .. join block.
M-x verilog-sk-module Insert a module .. (/*AUTOARG*/);.. endmodule block.
M-x verilog-sk-ovm-class Insert an OVM Class block.
M-x verilog-sk-uvm-class Insert an UVM Class block.
M-x verilog-sk-primitive Insert a primitive .. (.. );.. endprimitive block.
M-x verilog-sk-repeat Insert a repeat (..) begin .. end block.
M-x verilog-sk-specify Insert a specify .. endspecify block.
M-x verilog-sk-task Insert a task .. begin .. end endtask block.
M-x verilog-sk-while Insert a while (...) begin .. end block, prompting for details.
M-x verilog-sk-casex Insert a casex (...) item: begin.. end endcase block, prompting for details.
M-x verilog-sk-casez Insert a casez (...) item: begin.. end endcase block, prompting for details.
M-x verilog-sk-if Insert an if (..) begin .. end block.
M-x verilog-sk-else-if Insert an else if (..) begin .. end block.
M-x verilog-sk-comment Insert a comment block.
M-x verilog-sk-assign Insert an assign .. = ..; statement.
M-x verilog-sk-function Insert a function .. begin .. end endfunction block.
M-x verilog-sk-input Insert an input declaration, prompting for details.
M-x verilog-sk-output Insert an output declaration, prompting for details.
M-x verilog-sk-state-machine Insert a state machine definition, prompting for details.
M-x verilog-sk-inout Insert an inout declaration, prompting for details.
M-x verilog-sk-wire Insert a wire declaration, prompting for details.
M-x verilog-sk-reg Insert a register declaration, prompting for details.
M-x verilog-sk-define-signal Define signal under point as a register at the top of the module.
All key bindings can be seen in a Verilog-buffer with C-h b.
Key bindings specific to `verilog-mode-map' are:
Uses keymap `verilog-mode-map', which is not currently defined.
(fn)